Partial Set for Flip-Flops Based on State Requirement for Non-Scan BIST Scheme

Authors:
M. L. Flottes;C. Landrault;A. Petitqueux
Affiliations:
-;-;-
Venue:
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Year:
1999

Citing 0
Cited 4

Built-in generation of weighted test sequences for synchronous sequential circuits

DATE '00 Proceedings of the conference on Design, automation and test in Europe
A Unified DFT Approach for BIST and External Test

Journal of Electronic Testing: Theory and Applications
On the Use of Multiple Fault Detection Times in a Method for Built-In Test Pattern Generation for Synchronous Sequential Circuits

ETW '00 Proceedings of the IEEE European Test Workshop
At-Speed Logic BIST Using a Frozen Clock Testing Strategy

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a methodology for improving sequential circuit's testability in a pseudo-random testing environment. Our goal is to slightly modify the circuit under test with a DFT technique. For this, partial reset of circuit's flip-flops is performed during application of the test sequence. Flip-flop candidates for reset and their reset period are chosen according to a methodology based on identification of required test states for hard-to-detect faults. By increasing the probability to reach these states, we improve the fault coverage.