On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Static test sequence compaction based on segment reordering and accelerated vector restoration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Partial Set for Flip-Flops Based on State Requirement for Non-Scan BIST Scheme
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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The first time unit where a fault in a synchronous sequential circuit is detected by a given test sequence T0 is used by various procedures. One such procedure selects input sequences that are loaded onto an on-chip memory and used as seeds for built-in test pattern generation. Each input sequence is constructed based on a different fault f and is extracted from T0 around the first detection time of f. In this work, we extend this procedure to consider multiple time units where every target fault f is detected by T0 in order to select a shorter sequence based on f .The result is reduced storage requirements and test application time for this built-in test pattern generation approach.