Built-in generation of weighted test sequences for synchronous sequential circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Random test generation with input cube avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this paper a new test pattern generation method for the detection of delay faults is proposed. It can be seen as a directed random generation technique, and uses some original concepts from machine learning to generate delay fault detecting test pairs. First, a set of random test vectors is generated. Next, a learning tool working on those vectors provides relevant features of delay fault detecting test pairs. Finally, a set of new test vectors that are consistent with those features is generated. A comparison with other test generation techniques has been done on several circuits, and has shown the efficiency of our solution in terms of test sequence length and delay fault coverage.