Circuit synthesis with VHDL
VHDL: coding and logic synthesis with SYNOPSYS
VHDL: coding and logic synthesis with SYNOPSYS
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Inserting Scan at the Behavioral Level
IEEE Design & Test
Orthogonal Scan: Low-Overhead Scan for Data Paths
Proceedings of the IEEE International Test Conference on Test and Design Validity
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
Proceedings of the IEEE International Test Conference
VIUF '97 Proceedings of the 1997 VHDL International User's Forum (VIUF '97)
Synthesis-for-scan and scan chain ordering
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Scan Design Using Standard Flip-Flops
IEEE Design & Test
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-point insertion: scan paths through functional logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cost-free scan: a low-overhead scan path design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a methodology to insertscan paths in a functional Register Transfer Level (RTL)specification of a design that can exploit existingfunctional paths between sequential elements in theoriginal circuit for establishing scan chains. Theprimary objective for RTL scan insertion is to reduce thetime taken for DFT, and thus reduce the time to market.Additionally, building scan chains at the functional RT-Levelis expected to reduce the total area overheadintroduced by full scan without compromising the faultcoverage achieved. In addition, it often eliminates thedelay associated with the additional multiplexer as apart of a conventional scan-cell in high performancedesigns. Experimental results presented in this paperdemonstrate that the proposed method achieves theabove objectives while also achieving higher faultcoverages for most of the benchmark circuits considered.