VHDL: coding and logic synthesis with SYNOPSYS

Synthesis of Scan Chains for Netlist Descriptions at RT-Level

Journal of Electronic Testing: Theory and Applications

Embedded Computer Architecture and Automation

Computer

Embedded Computing: New Directions in Architecture and Automation

HiPC '00 Proceedings of the 7th International Conference on High Performance Computing

On RTL Scan Design

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Implementation of the super-systolic array for convolution

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference