Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
VLSI array processors
VHDL: coding and logic synthesis with SYNOPSYS
VHDL: coding and logic synthesis with SYNOPSYS
Digital Systems Design with VHDL and Synthesis
Digital Systems Design with VHDL and Synthesis
VHDL Modeling for Digital Design Synthesis
VHDL Modeling for Digital Design Synthesis
General-Purpose Systolic Arrays
Computer
Design of an application-specific PLD architecture
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal
International Journal of Circuit Theory and Applications
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High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The architecture of systolic array with its cells consisting of another systolic array is to be called super-systolic array.In this paper we propose a scalable super-systolic array architecture which shows high-performance and can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture.