A VHDL SGRGAM model for the validation environment of a high performance graphic processor
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Behavioral Model of Analog Circuits for Nonvolatile Memories with VHDL-AMS
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Implementation of the super-systolic array for convolution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
"Chameleon" software defined control platform
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
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From the Publisher:The purpose of VHDL Modeling for Digital Design Synthesis is to introduce VHSIC Hardware Description Language (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that permitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the implementation technology. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. This book covers the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. VHDL Modeling for Digital Design Synthesis is designed for working professionals as well as for graduate or undergraduate students. Readers can use this book to get acquainted with VHDL and to learn how it can be used in modeling of digital designs.