VLSI array processors
Designing with FPGAs and CPLDs
Designing with FPGAs and CPLDs
General-Purpose Systolic Arrays
Computer
Computational Neurobiology Meets Semiconductor Engineering
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
Reversible Logic Synthesis
Implementation of the super-systolic array for convolution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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This paper presents a new application-specific PLD architecture which adopts a bit-level super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. The bit-level super-systolic array whose cells contain another systolic array is ideal for newly proposed PLD architecture in terms of area efficiency and clock speed as it limits the routing requirement in a PLD to local interconnections between Logic Units and to global interconnections between Logic Modules. The maximum clock cycle is limited only by one AND gate and one full adder.