Massively parallel systolic-array architectures for 2d IIR polyphase space–time plane-wave beam digital filters

  • Authors:

  • Arjuna Madanayake;Thushara K. Gunaratne;Len T. Bruton

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Akron 302, Buchtel Common, Akron, OH 44325-3904, U.S.A.;Department of Electrical and Computer Engineering, University of Calgary, 2500 University Drive NW, Calgary, AB, Canada T2N 1N4;(Fellow, IEEE) Department of Electrical and Computer Engineering, University of Calgary, 2500 University Drive NW, Calgary, AB, Canada T2N 1N4

  • Venue:
  • International Journal of Circuit Theory and Applications
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

A systolic architecture has recently been proposed for implementing two-dimensional infinite impulse response (IIR) space–time beam plane-wave filters at a throughput of one-frame-per-clock–cycle for such applications as real-time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M-frames-per-clock-cycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look-ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock-cycle limit of the very large-scale integration (VLSI) technology, thereby potentially allowing multi-GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array-based real-time prototype is described, tested and verified for the two-phase case (M = 2) at a technology-limited clock frequency of 50 MHz which corresponds to a throughput of 100 million-frames-per-clock–cycle. Copyright © 2010 John Wiley & Sons, Ltd.