Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
International Journal of Circuit Theory and Applications
| Hi-index | 35.68 |
An improved systolic architecture for two-dimensional infinite-impulse response (IIR) and finite-impulse-response (FIR) digital filters is presented. Comparisons with recently published work are made. When compared with the architecture of M.A. Sid-Ahmed (1989), a substantial reduction in the number of delay elements is observed. This reduction is of the order of 102 for a 2-D IIR filter and equals N+1 for an Nth-order 2-D FIR filter. The clock period has been made independent of the order of the filter. The speed-up factor is the maximum achievable and is independent of the filter order. Comparison with the work of S. Sunder et al. (1990) shows an improvement in the latency of the systolic array, which has been reduced from 1 to 0. A reduction of N+1 delay elements has been achieved for the FIR filter. An error analysis for the architecture is made