Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture

Authors:
D. V. Poornaiah;P. V. A. Mohan
Affiliations:
-;-
Venue:
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Year:
1995

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Abstract

In this paper, we introduce a novel VLSI concurrent multiplier-accumulator (MAC) architecture based on the extension of the widely used second order modified Booth's algorithm. Two efficient algorithms: sign extension bits minimization algorithm (SEBMA) and sign-bit updating algorithm are also presented for minimising the number of sign extension bits to be added and also for dealing with the input operands of arbitrary word-lengths involving different data formats for 3- as well as multi-bit recoded parallel multipliers and MACs. A salient feature of the proposed MAC cell is attributed to its ability in performing the different computations involved : (i) multiplication, (ii) accumulation (add or subtract), (iii) addition of the compensating carry-bits due to the presence of the negative partial product terms and (iv) addition of the minimized number of sign extension bits (computed through SEBMA) concurrently thereby achieving a reduction of 50% in the computation time along with 15% savings in the area when compared with the conventional MAC cells. In order to verify the proposed theory, a 3-bit recoded CMOS 16-gbit MAC cell is designed based on 1 /spl mu/m CMOS standard cell technology rules featuring a worst case cycle time of 35 ns at a capacitive load of 50 pf.