A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications

Authors:
D. V. Poornaiah;P. V. A. Mohan
Affiliations:
-;-
Venue:
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Year:
1996

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Abstract

In this paper, an efficient algorithm for concurrent computation of two real multiplications and/or two real additions usually required for high-throughput image and video coding applications is described. The proposed algorithm is mapped onto a novel concurrent dual multiplier-dual adder cell based on carry-save 4:2 compressors. A detailed performance analysis of the the proposed cell shows reductions ranging from 15% to 60% in the computation time and area when compared with the conventional processing elements making it highly attractive for VLSI implementation.