Circuit synthesis with VHDL
VHDL: coding and logic synthesis with SYNOPSYS
VHDL: coding and logic synthesis with SYNOPSYS
Advanced ASIC Chip Synthesis: Using Synopsys' Design Compiler and PrimeTime
Advanced ASIC Chip Synthesis: Using Synopsys' Design Compiler and PrimeTime
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
Inserting Scan at the Behavioral Level
IEEE Design & Test
Orthogonal Scan: Low-Overhead Scan for Data Paths
Proceedings of the IEEE International Test Conference on Test and Design Validity
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
Proceedings of the IEEE International Test Conference
VIUF '97 Proceedings of the 1997 VHDL International User's Forum (VIUF '97)
Synthesis-for-scan and scan chain ordering
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-point insertion: scan paths through functional logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cost-free scan: a low-overhead scan path design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
A graph-based approach to optimal scan chain stitching using RTL design descriptions
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.