Circuit synthesis with VHDL

Towards maximising the use of structural VHDL for synthesis

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Synthesis of Scan Chains for Netlist Descriptions at RT-Level

Journal of Electronic Testing: Theory and Applications

Inserting Scan at the Behavioral Level

IEEE Design & Test

A Reconfigurable Hardware Tool for High Speed Network Simulation

TOOLS '98 Proceedings of the 10th International Conference on Computer Performance Evaluation: Modelling Techniques and Tools

Fast prototyping of memory models in VHDL for hardware emulation

RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)

On RTL Scan Design

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation

Proceedings of the conference on Design, automation and test in Europe - Volume 3

A genetic_FPGA algorithm path planning of an autonomous mobile robot

MAMECTIS'08 Proceedings of the 10th WSEAS international conference on Mathematical methods, computational techniques and intelligent systems