Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Circuit synthesis with VHDL
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
A prototype VLSI chip architecture for JPEG image compression
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Pipelined Fast 2-D DCT Architecture for JPEG Image Compression
Proceedings of the 14th symposium on Integrated circuits and systems design
A real-time and parametric parallel video compression architecture using FPGA
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
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This paper presents a project space exploration on the baseline JPEG compressor proposed and implemented in previous works. This exploration took as basis the substitution of the operators used in the 2-D DCT calculation architecture of the compressor and the consequent evaluation of impact in terms of performance and resources utilization. This substitution was made with main focus in the carry lookahead, hierarchical carry lookahead and carry select architectures, with the objective to increase the JPEG compressor performance. As the compressor architecture was designed in an hierarchical mode the operators substitution was an activity quite simple, because it has not involved the other hierarchy levels. The operators were described in VHDL, synthesized and validated. They were inserted in the 2-D DCT architecture for synthesis in the whole module. The 2-D DCT was synthesized for an Altera FPGA. With this project space exploration, the highest performance obtained for the 2-D DCT was 23% higher than the original, using 11% more logic cells.