Synthesis of Scan Chains for Netlist Descriptions at RT-Level
Journal of Electronic Testing: Theory and Applications
Efficient Test Mode Selection & Insertion for RTL-BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A graph-based approach to optimal scan chain stitching using RTL design descriptions
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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Synthesis of ASICs from Register Transfer Level(RTL) source is often a bottom up iterative process where synthesis process is carefully controlled to produce a gate- level design which meets the desired constraints. Test logic, such as Built-in Self Test(BIST), is typically inserted at the gate level. This may cause new violations of timing/area goals thus causing an expensive cycle of re-optimization on the complete chip at the end of the design process. Performing BIST logic insertion at the RT level source allows synthesis technology to consider test logic while optimizing to meet area/timing goals thus avoiding an expensive re-optimization. It also provides opportunity for sharing of functional and test logic. Scan Based BIST utilizes scan chains to apply random vectors and observe signal values within the random logic. This paper will describe techniques for inserting scan chains at the RTL- VHDL source in the context of Scan BIST and report its impact on design optimization and fault coverage.