A graph-based approach to optimal scan chain stitching using RTL design descriptions

Authors:
Lilia Zaourar;Yann Kieffer;Chouki Aktouf
Affiliations:
SOC Department, University Pierre and Marie Curie, Paris Cedex 05, France;LCIS, Grenoble Institute of Technology and University of Grenoble, Valence Cedex, France;DeFacTo Technologies, Moirans, France
Venue:
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
Year:
2012

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Abstract

The scan chain insertion problem is one of the mandatory logic insertion design tasks. The scanning of designs is a very efficient way of improving their testability. But it does impact size and performance, depending on the stitching ordering of the scan chain. In this paper, we propose a graph-based approach to a stitching algorithm for automatic and optimal scan chain insertion at the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity information from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem to determine the best scan-stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis and implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial.