A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
Proceedings of the 37th Annual Design Automation Conference
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Synthesis of Scan Chains for Netlist Descriptions at RT-Level
Journal of Electronic Testing: Theory and Applications
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An RTL Methodology to Enable Low Overhead Combinational Testing
EDTC '97 Proceedings of the 1997 European conference on Design and Test
High-Level Synthesis for Orthogonal Scan
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ITC '01 Proceedings of the 2001 IEEE International Test Conference
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Register-transfer level functional scan for hierarchical designs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A study on insuring the full reliability of finite state machine
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartII
A New Design-for-Testability Method Based on Thru-Testability
Journal of Electronic Testing: Theory and Applications
A graph-based approach to optimal scan chain stitching using RTL design descriptions
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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This paper presents H-SCAN, a practical testing methodology that can be easily applied to a high-level design specification. H-SCAN allows the use of combinational test patterns without the high area and test application time overheads associated with full-scan testing. Connectivities between registers existing in an RT-level design are exploited to reduce the area overhead associated with implementing a scan scheme. Test application time is significantly reduced by using the parallelism inherent in the design, and eliminating the pin constraint of parallel scan schemes by analyzing the test responses on-chip using existing comparators. The proposed method also includes generating appropriate sequential test vectors from combinational test vectors generated by a combinational ATPG program. Application of H-SCAN to RT-level designs and fault simulation using the test patterns generated by H-SCAN shows fault coverage comparable to full-scan testing, with significant reduction in test area overhead and test application time when compared to a traditional gate-level full-scan implementation.