An RTL Methodology to Enable Low Overhead Combinational Testing

Authors:
Subhrajit Bhattacharya;Sujit Dey;Bhaskar Sengupta
Affiliations:
C&C Research Laboratories, NEC USA, Princeton, NJ;C&C Research Laboratories, NEC USA, Princeton, NJ;C&C Research Laboratories, NEC USA, Princeton, NJ
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

Citing 13
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Abstract

This paper introduces a low overhead test methodology, RT-SCAN, applicable to RT Level designs. The methodology enables using combinational test patterns for testing the circuit, as done by traditional full-scan or parallel-scan schemes. However, by exploiting existing connectivity of registers through multiplexors and functional units, RT-SCAN reduces area overhead and test application times significantly compared to full-scan and parallel-scan schemes. Unlike most of the existing high-level test synthesis and test generation schemes which can be most effectively applied to data-flow/arithmetic intensive designs like DSPs and processor designs, the RT-SCAN test scheme can be applied to designs from any application domain, including control-flow intensive designs.