New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency

Authors:
Debesh Kumar Das;Satoshi Ohtake;Hideo Fujiwara
Affiliations:
Department of Comp. Sc. and Engg., Jadavpur University, Kolkata-700 032, India. debeshd@hotmail.com;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5, Takayama-Cho, Ikoma, Nara 630-0101, Japan. ohtake@is.aist-nara.ac.jp;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5, Takayama-Cho, Ikoma, Nara 630-0101, Japan. fujiwra@is.aist-nara.ac.jp
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2004

Citing 7
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Abstract

This paper suggests three techniques on non-scan DFT of sequential circuits. The proposed techniques guarantee 100% fault efficiency by using combinational ATPG tool. In all the techniques, an additional circuit called CRIS is proposed to reach unreachable states on the state register of a machine. The second and third techniques use an additional hardware DL to uniquely identify a state appearing in a state register. The design of DL is universal. Test length and hardware overhead outperform the similar approaches.