Logic testing and design for testability
Logic testing and design for testability
Finite state machine synthesis with embedded test function
Journal of Electronic Testing: Theory and Applications
Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Partial Scan Design Based on State Transition Modeling
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Proceedings of the IEEE International Test Conference on Test and Design Validity
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test function embedding algorithms with application to interconnected finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency
Journal of Electronic Testing: Theory and Applications
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This paper presents a non-scan design-for-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. In the proposed method, at-speed test application can be performed and the test application time is shorter than previous methods. Moreover, experimental results show the area overhead is low.