Digital logic testing and simulation
Digital logic testing and simulation
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
NOVA: state assignment of finite state machines for optimal two-level logic implementations
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Design for Testability Using State Distances
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Initialization of Sequential Circuits and its Application to ATPG
Journal of Electronic Testing: Theory and Applications
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Synthesis for Logical Initializability of Synchronous Finite State Machines
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.2 On Synchronizing Sequences and Test Sequence Partitioning
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
On the initialization of sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 14.98 |
It is shown that a finite-state machine, whose state encoding is obtained only to reduce the amount of logic in the final implementation, may not be initializable by a logic simulator or a test generator even when the circuit is functionally initializable (i.e. has synchronizing sequences). A fault simulator or a sequential circuit test generator that assumes all memory elements initially to be in the unknown state will be totally ineffective for such a design. Proper consideration for initializability during state assignment and logic optimization can guarantee the success for gate-level analysis tools. The conditions for initializability of finite-state machines are derived, and an automatic state assignment algorithm for logic minimality and initializability is given. Experimental results show that, in most cases, this method does not require more hardware than the other methods that may produce an uninitializable design. A partial reset technique, recommended for machines without a synchronizing sequence, is also discussed.