Digital logic testing and simulation
Digital logic testing and simulation
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
Finite state machine synthesis with embedded test function
Journal of Electronic Testing: Theory and Applications
Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Parial Scan Using Reverse Direction Empirical Testability
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan
ATS '96 Proceedings of the 5th Asian Test Symposium
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
An optimized testable architecture for finite state machines
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
MACHETE: synthesis of sequential machines for easy testability
EURO-DAC '91 Proceedings of the conference on European design automation
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Test Point Placement to Simplify Fault Detection
IEEE Transactions on Computers
A partition and resynthesis approach to testable design of large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Sequential circuit testing is an active research area due to its applicability, its practicality, and its complexity. This paper gives an overview of the sequential automatic test pattern generation approaches and the classical and more recent design-for-testability methods. However, recent trend is to move towards synthesis-for-testability (SFT) approach. In this paper, we describe some of the work done by others as well as our current research using SFT techniques. In particular, the ability to perform SFT on large sequential circuits is discussed.