Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design for Testability Using State Distances
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
IEEE Transactions on Computers
On the use of reset to increase the testability of interconnected finite-state machines
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A New Design-for-Testability Method Based on Thru-Testability
Journal of Electronic Testing: Theory and Applications
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We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. First, we develop a test machine embedding technique for a given gate-level implementation of a finite state machine. The test machine states are mapped onto the states of the given circuit such that a minimum number of new state variable dependencies are introduced. The composite function is optimized. Experimental results show that our method yields testable machine implementations that have lower area than the corresponding full scan designs. The test generation complexity for our machine implementation is the same as that for a full scan design. To apply the method to large gate-level designs, we partition the circuit into interconnected finite-state machines. Each component state machine can be specified either as its gate-level implementation or as the extracted state diagram. We incorporate test functions into each component finite state machine such that the entire interconnection of the augmented components has the same testability properties as the product machine with a single test function. ISCAS '89 benchmark circuits are partitioned into component finite state machines using a new testability-directed partitioning algorithm. Again, our embedding procedure results in testable circuits that have lower area than the corresponding full scan designs