NOVA: state assignment of finite state machines for optimal two-level logic implementations
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
An architecture for synthesis of testable finite state machines
EURO-DAC '90 Proceedings of the conference on European design automation
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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Test generation for sequential machines is known to be computationally expensive. We present a scheme, called MACHETE (MACHines for Easy TEstability), for synthesizing easily testable architectures for sequential machines by adding some state transitions and their associated output vectors to the state transition table. This is done to make the internal states of the machine easily controllable as well as observable. This can enable us to obtain a high fault coverage in reasonable amounts of CPU time.