Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
Minimum length synchronizing sequences of finite state machine
DAC '93 Proceedings of the 30th international Design Automation Conference
A synthesis system for testable and area-efficient finite state machines
A synthesis system for testable and area-efficient finite state machines
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Application of Homing Sequences to Synchronous Sequential Circuit Testing
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
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Abstract: The goal is to synthesize an FSM with the objective to minimize the number of scanned flip-flops while requiring a minimum number of system clocks to reach the synchronizable state. An algorithm for selecting state variables for scanning while minimizing the length of the synchronizing sequence based on the reverse-order-search technique is presented. Extra transitions may be required to avoid possible lock-in conditions if the initial state is an invalid state for the machines where the number of states is not a power of 2. Experimental results show that the proposed method guarantees synchronizability and testability through the proper state assignment with reasonable hardware overhead for the benchmark circuits.