Introduction to algorithms
Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Exact calculation of synchronization sequences based on binary decision diagrams
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Minimum length synchronizing sequences of finite state machine
DAC '93 Proceedings of the 30th international Design Automation Conference
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
On the Initialization of Sequential Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented in this paper. This method is based on structural decomposition of the circuit, and can handle both logical (using X-value simulation) and functional initializability. The routines developed are then used for ATPG of sequential circuits. A “pre-test” sequence that initializes the good and as many of the faulty machines as possible is generated and used in conjunction with CRIS [5], a simulation based sequential ATPG program, to generate a test set for the circuit.