An automatic rectilinear partitioning procedure for standard cells
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Technology adaption in logic synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Efficient tree pattern matching (extended abstract): an aid to code generation
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Optimal Code Generation for Expression Trees
Journal of the ACM (JACM)
Code Generation for a One-Register Machine
Journal of the ACM (JACM)
Code Generation for Expressions with Common Subexpressions
Journal of the ACM (JACM)
Journal of the ACM (JACM)
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A high level synthesis tool for MOS chip design
DAC '84 Proceedings of the 21st Design Automation Conference
LSS: a system for production logic synthesis
IBM Journal of Research and Development
Anatomy of a hardware compiler
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Multi-level logic synthesis using communication complexity
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Test function specification in synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithms for library-specific sizing of combinational logic
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A technology mapping method based on perfect and semi-perfect matchings
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing optimization on mapped circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Mapping switch-level simulation onto gate-level hardware accelerators
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A heuristic method for FPGA technology mapping based on the edge visibility
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Bridging high-level synthesis to RTL technology libraries
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
Partitioning by regularity extraction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Characterization of Boolean functions for rapid matching in FPGA technology mapping
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An improved synthesis algorithm for multiplexor-based PGA's
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On the circuit implementation problem
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
BDDMAP: a technology mapper based on a new covering algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Boolean matching in logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Automatic technology mapping for generalized fundamental-mode asynchronous designs
DAC '93 Proceedings of the 30th international Design Automation Conference
MIM: logic module independent technology mapping for design and evaluation of antifuse-based FPGAs
DAC '93 Proceedings of the 30th international Design Automation Conference
Towards optimal system-level design
DAC '93 Proceedings of the 30th international Design Automation Conference
On testing delay faults in macro-based combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
LP based cell selection with constraints of timing, area, and power consumption
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Decomposition methods for library binding of speed-independent asynchronous designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On error correction in macro-based circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Boolean matching of sequential elements
DAC '94 Proceedings of the 31st annual Design Automation Conference
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New ideas for solving covering problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Procedure exlining: a transformation for improved system and behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Delay minimal decomposition of multiplexers in technology mapping
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A new method towards achieving global optimality in technology mapping
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Synthesis using sequential functional modules (SFMs)
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Hmap: a fast mapper for EPGAs using extended GBDD hash tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An algorithm for the allocation of functional units from realistic RT component libraries
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Inverter minimization in multi-level logic networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A simple algorithm for fanout optimization using high-performance buffer libraries
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Boolean matching for full-custom ECL gates
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generalized matching from theory to application
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1997 international symposium on Physical design
The future of logic synthesis and physical design in deep-submicron process geometries
Proceedings of the 1997 international symposium on Physical design
Fast module mapping and placement for datapaths in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
Boolean matching for large libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
M32: a constructive multilevel logic synthesis system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
Exact tree-based FPGA technology mapping for logic blocks with independent LUTs
DAC '98 Proceedings of the 35th annual Design Automation Conference
MILO: a microarchitecture and logic optimizer
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
BECOME: behavior level circuit synthesis based on structure mapping
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A kernel-finding state assignment algorithm for multi-level logic
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
On accelerating pattern matching for technology mapping
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Technology mapping for domino logic
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic detection of recurring operation patterns
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
A tutorial on logic synthesis for lookup-table based FPGAs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient Boolean function matching
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An &agr;-approxmimate algorithm for delay-constraint technology mapping
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Area and search space control for technology mapping
Proceedings of the 37th Annual Design Automation Conference
Watermarking while preserving the critical path
Proceedings of the 37th Annual Design Automation Conference
An integrated algorithm for combined placement and libraryless technology mapping
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Copy detection for intellectual property protection of VLSI designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Technology mapping and retargeting for field-programmable analog arrays
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Technology mapping for minimizing gate and routing area
Proceedings of the conference on Design, automation and test in Europe
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
A new structural pattern matching algorithm for technology mapping
Proceedings of the 38th annual Design Automation Conference
New frontiers in logic synthesis: a report on IWLS 89
ACM SIGDA Newsletter
Low-power technology mapping for mixed-swing logic
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology mapping algorithms for domino logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic Synthesis and Verification
Technology-based transformations
Logic Synthesis and Verification
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computation in the Context of Transport Triggered Architectures
International Journal of Parallel Programming
Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
A Model-Based Expert System for Digital System Design
IEEE Design & Test
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
Technology Mapping in Circuit Design Aids
IEEE Design & Test
Efficient Multiplexer Synthesis Techniques
IEEE Design & Test
BETSY: synthesizing circuits for a specified BIST environment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Bounding the efforts on congestion optimization for physical synthesis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
Design and synthesis of dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Improved technology mapping using a new approach to Boolean matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Design reuse through high-level library mapping
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Rapid Gate Matching with Don't Cares
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code
EDTC '97 Proceedings of the 1997 European conference on Design and Test
AATMA: an algorithm for technology mapping for antifuse-based FPGAs
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Technology Mapper for Xilinx FPGAs
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Addressing Early Design-For-Test Synthesis in a Production Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
A new synthesis technique for multilevel combinational circuits
EURO-DAC '90 Proceedings of the conference on European design automation
An architecture for synthesis of testable finite state machines
EURO-DAC '90 Proceedings of the conference on European design automation
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A predictive distributed congestion metric and its application to technology mapping
Proceedings of the 2004 international symposium on Physical design
High level techniques for power-grid noise immunity
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Technology mapping and packing for coarse-grained, anti-fuse based FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Advanced technology mapping for standard-cell generators
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Efficient metrics and high-level synthesis for dynamically reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
IEEE Transactions on Computers
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
Logical effort based technology mapping
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Logic optimization using rule-based randomized search
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast Boolean Matching with Don't Cares
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Techniques for improved placement-coupled logic replication
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
Proceedings of the 43rd annual Design Automation Conference
Performance-driven technology mapping with MSG partition and selective gate duplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAG based library-free technology mapping
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Pattern-based behavior synthesis for FPGA resource reduction
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Near-optimal instruction selection on dags
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Smart Enumeration: A Systematic Approach to Exhaustive Search
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling Service Level Agreements with Binary Decision Diagrams
ICSOC-ServiceWave '09 Proceedings of the 7th International Joint Conference on Service-Oriented Computing
Transistor sizing for large combinational digital CMOS circuits
Integration, the VLSI Journal
Fault-tolerant synthesis using non-uniform redundancy
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Covering strategies for library free technology mapping
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Automated logic synthesis of random pattern testable circuits
ITC'94 Proceedings of the 1994 international conference on Test
TRECO: dynamic technology remapping for timing engineering change orders
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Are logic synthesis tools robust?
Proceedings of the 48th Design Automation Conference
UbiComp'06 Proceedings of the 8th international conference on Ubiquitous Computing
Generalized SAT-sweeping for post-mapping optimization
Proceedings of the 49th Annual Design Automation Conference
Experimentally driven verification of synthetic biological circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
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Technology binding is the process of mapping a technology independent description of a circuit into a particular technology. This paper outlines a formalism of this problem and offers a solution to the problem in terms of matching patterns, describing technology specific cells and optimizations, against a technology independent circuit represented as a directed acyclic graph. This solution is implemented in DAGON. DAGON rests on a firm algorithmic foundation, and is able to guarantee locally optimal matches against a set of over three thousand patterns. DAGON is an integral part of a synthesis system that has been found to provide industrial quality solutions to real circuit design problems.