DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The MICON system for computer design
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Introduction to algorithms
Bridging high-level synthesis to RTL technology libraries
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
An algorithm for the allocation of functional units from realistic RT component libraries
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
MILO: a microarchitecture and logic optimizer
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A systematic analysis of reuse strategies for design of electronic circuits
Proceedings of the conference on Design, automation and test in Europe
Cross-level hierarchical high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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We present high-level library mapping (HLLM), a technique that permits reuse of complex databook components (specifically ALUs) in architectural synthesis. We describe a dynamic programming formulation of HLLM, demonstrate the versatility of our approach on a variety of libraries and compare HLLM for ALUs with the traditional logic-synthesis approach. Our experiments show that HLLM for ALUs outperforms logic-synthesis in area, delay and runtime, indicating that HLLM is a promising approach for reuse of datapath components in architectural synthesis.