High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Automatic module allocation in high level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
Timing preserving interface transformations for the synthesis of behavioral VHDL
EURO-DAC '94 Proceedings of the conference on European design automation
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Productivity issues in high-level design: are tools solving the real problems?
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
VHDL based design methodology for hierarchy and component re-use
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Library insertion and reuse of datapath components in high-level synthesis
Library insertion and reuse of datapath components in high-level synthesis
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Design reuse through high-level library mapping
EDTC '95 Proceedings of the 1995 European conference on Design and Test
CASCH: a scheduling algorithm for "high level"-synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Quadratic zero-one programming-based synthesis of application-specific data paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synchronization detection for multi-process hierarchical synthesis
Proceedings of the 11th international symposium on System synthesis
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified systems while preserving the hierarchical structure. After synthesis of each subsystem the determined component schedule and the synthesized RT-structure are added to its algorithmic specification. This provides an automatic selection of optimized complex components. Furthermore, the component schedule enables the sharing of unused subcomponents across different hierarchical levels of the design.