On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing preserving interface transformations for the synthesis of behavioral VHDL
EURO-DAC '94 Proceedings of the conference on European design automation
Performance-driven MCM partitioning through an adaptive genetic algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Transmogrifier-2: a 1 million gate rapid prototyping system
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Cross-level hierarchical high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Frontier: A Fast Placement System for FPGAs
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
FPGA-Based Prototyping for Product Definition
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Truly Rapid Prototyping Requires High-Level Synthesis
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
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In this paper we present a new design flow for efficient hardware implementation of behavioral system specifications at algorithmic level into heterogeneous multi-FPGA (Field-Programmable Gate Arrays) rapid prototyping systems. We discuss the benefits of coupling the high-level synthesis tool CADDY-II and the partitioning and mapping environment PuMA, which is designed for optimized implementation of RT-level (Register-Transfer) netlists into multi-FPGA architectures. With our new approach, rapid prototyping and in-circuit verification in earliest design phases are enabled. Due to short implementation times and precise back annotation accomplished by a close coupling of the tools, more design iterations and thus better design space exploration is possible.