Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
System synthesis using behavioural descriptions
EURO-DAC '90 Proceedings of the conference on European design automation
Automatic module allocation in high level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An approach for extracting RT timing information to annotate algorithmic VHDL specifications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Verification by simulation comparison using interface synthesi
Proceedings of the conference on Design, automation and test in Europe
Cross-level hierarchical high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
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It is the goal of the recently developed and herewith presented scheduling algorithm to optimize the timing behaviour within automated circuit synthesis. The algorithm is a part of the CADDY-Synthesis-System (CAddy SCHeduling). Basis is a list scheduling algorithm which is controlled by a heuristic rating function. The allocated resources can be modelled in a flexible and detailed manner in order to specify component types for several different operations as well as different component types for the same operation. It is a special feature of this scheduling algorithm that the assignment of operations to component types is decided during the scheduling.