An approach for extracting RT timing information to annotate algorithmic VHDL specifications

Symbolic Boolean manipulation with ordered binary-decision diagrams

ACM Computing Surveys (CSUR)

Timing preserving interface transformations for the synthesis of behavioral VHDL

EURO-DAC '94 Proceedings of the conference on European design automation

CHU spaces: a model of concurrency

CHU spaces: a model of concurrency

A graphical data management system for HDL-based ASIC design projects

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

An Approach for a Dynamic Generation/Validation System for the Functional Simulation Considering Timing Constraints

EDTC '96 Proceedings of the 1996 European conference on Design and Test

CASCH: a scheduling algorithm for "high level"-synthesis

EURO-DAC '91 Proceedings of the conference on European design automation