VHDL based design methodology for hierarchy and component re-use

  • Authors:
  • Polen Kission;Hong Ding;Ahmed A. Jerraya

  • Affiliations:
  • TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cédex, France;TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cédex, France;TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cédex, France

  • Venue:
  • EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
  • Year:
  • 1995

Quantified Score

Hi-index 0.00

Visualization

Abstract