Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Synchronization detection for multi-process hierarchical synthesis
Proceedings of the 11th international symposium on System synthesis
Improved interconnect sharing by identity operation insertion
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Cross-level hierarchical high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a novel technique for the synthesis of complex multifunctional units is presented. Given a set of functions, the goal is to minimize the area cost of a unit that can execute these functions. A set of primitive functional units is allocated and shared between operations which belong to different functions. In the presented approach, a bipartite matching-based technique is extended with a quadratic cost function which allows for a much more accurate modeling of interconnect cost compared to previous approaches. In the optimization process, functional unit type selection, instance allocation, and instance assignment are performed simultaneously. As an extension of the technique, a set of constraints which exclude solutions with false combinatorial cycles are also presented. The technique finds its main applicability in the synthesis of custom accelerator data paths in high throughput signal processing applications, as required in video, image processing, front end speech processing, and user-end telecom. In addition, it can be applied in the synthesis of the data path of domain-specific instruction set processors. Experiments show that highly optimized results can be obtained within acceptable CPU times