Redundant operator creation: a scheduling optimization technique
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Optimizing resource utilization and testability using hot potato techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
A new optimization technique for improving resource exploitation and critical path minization
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Area optimization of multi-functional processing units
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Quadratic zero-one programming-based synthesis of application-specific data paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective techniques for the generalized low-power binding problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Increasing hardware efficiency with multifunction loop accelerators
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A global interconnect reduction technique during high level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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This paper presents an approach to reduce interconnect cost by insertion of identity operations in a CDFG. Other than previous approaches, it is based on systematic pattern analysis and automated transformation selection. The cost function controlling transformation selection is derived with statistical experiments and is optimized using practical benchmarks. The results show significantly reduced interconnect cost for most register architectures and application examples.