DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Inverter minimization in multi-level logic networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Boolean matching for large libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
LECTOR: a technique for leakage reduction in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper compares dynamic methodologies for technology mapping targeting virtual libraries available through cell generators. Dynamic covering is reputed for being exact, but in fact its exactness depends on the ordering of the initial subject description. A new dynamic approach exploiting reordering of the initial description is proposed and compared to the traditional dynamic approach from SIS. The approach we propose is exact with respect to the number of multi-input complex gates. Main contributions are the description of the effect of reordering and the comparison between the approaches. A tool dedicated to library free technology mapping has been implemented to demonstrate the significance of the method.