DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic synthesis
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On accelerating pattern matching for technology mapping
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Journal of the ACM (JACM)
Efficient string matching: an aid to bibliographic search
Communications of the ACM
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Advanced technology mapping for standard-cell generators
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Performance-driven technology mapping with MSG partition and selective gate duplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A robust asynchronous early output full adder
WSEAS Transactions on Circuits and Systems
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In this paper, a new structural matching algorithm for technology mapping is proposed. The algorithm is based on a key observation that the matches for a node in a subject Boolean network are related to the matches for its children. The structural relationships between the library cells are modeled using a lookup table. The proposed method is fast, has low memory usage, and is easy to implement. Experimental results show speedups of 20x over Matsunaga's fast mapping approach, and orders of magnitude over SIS, with the same or slightly better results, and much lower memory utilization.