DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A new structural pattern matching algorithm for technology mapping
Proceedings of the 38th annual Design Automation Conference
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In this paper, a new algorithm for technology mapping aiming standard-cell generators is proposed. The proposed method has features that explore several AND/OR circuit decompositions by using a n-ary tree representation of the circuit. In the covering step, the cell that leads to the smaller depth increase is chosen. Depth calculation is not limited to the subject tree and takes into account all previously mapped trees representing sub-expressions used as inputs. Experimental results show gains in circuit depth measured by the number of gates in series, as well as in area measured by transistor count when compared to SIS mapping approach using the same libraries. The gain in circuit depth translates to better timing as verified by spice simulations.