Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The first asynchronous microprocessor: the test results
ACM SIGARCH Computer Architecture News
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Delay-insensitive multi-ring structures
Integration, the VLSI Journal - Special issue on asynchronous systems
A new structural pattern matching algorithm for technology mapping
Proceedings of the 38th annual Design Automation Conference
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Coping with The Variability of Combinational Logic Delays
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Efficient synthesis of speed-independent combinational logic circuits
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Asynchronous Nano-Electronics: Preliminary Investigation
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
ACSD '10 Proceedings of the 2010 10th International Conference on Application of Concurrency to System Design
Robust asynchronous implementation of Boolean functions on the basis of duality
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
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A robust asynchronous full adder design corresponding to early output logic, synthesized using the elements of a standard cell library is presented in this paper. As the name suggests, the adder ensures gate orphan freedom and neatly fits into the self-timed system architecture. In comparison with many of the indicating full adder designs, which can be embedded in the self-timed system, it is found that the proposed full adder enables reduction in latency by 20.7%, occupies lesser area by 15.4% and features minimized average power dissipation by 8.6% against the best design metrics of its counterparts. These design estimates correspond to simulation results of the 32-bit carry-ripple adder circuit; derived by targeting a high-speed 130nm bulk CMOS process technology. Also, the proposed full adder facilitates a faster reset and the return-to-zero for the fundamental carry-propagate topology is achieved with only two full adder delays.