Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation

Authors:
Cheoljoo Jeong;Steven M. Nowick
Affiliations:
-;-
Venue:
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Year:
2008

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Abstract

This paper describes a method of synthesising asynchronous circuits based on the Handshake Circuit paradigm but employing a data-driven, rather than the control-driven, style. This approach attempts to combine the performance advantages of data-driven ...