Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Integration, the VLSI Journal
Self-timed rings and their application to division
Self-timed rings and their application to division
Delay-insensitive multi-ring structures
Integration, the VLSI Journal - Special issue on asynchronous systems
Evaluation of function blocks for asynchronous design
EURO-DAC '94 Proceedings of the conference on European design automation
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Logically Determined Design: Clockless System Design with NULL Convention Logic
Logically Determined Design: Clockless System Design with NULL Convention Logic
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
QDI decomposed DIMS method featuring homogeneous/heterogeneous data encoding
ICANCM'11/ICDCC'11 Proceedings of the 2011 international conference on applied, numerical and computational mathematics, and Proceedings of the 2011 international conference on Computers, digital communications and computing
A robust asynchronous early output full adder
WSEAS Transactions on Circuits and Systems
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Design of a low-power embedded processor architecture using asynchronous function units
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Dual-rail asynchronous logic multi-level implementation
Integration, the VLSI Journal
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Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward way is to structurally map the gates in a synchronous netlist to their functionally equivalent modules which use delay-insensitive codes. Different trade-offs exist in previous methods between the overheads of the implementations and their robustness. The aim of this paper is to optimise the area of asynchronous circuits using partial acknowledgement concept. We employ this concept in two design flows, which are implemented in a software tool to evaluate the efficiency of the method. The benchmark results show the average reduction in area by 28% and in the number of inter-functional module wires that require timing verification by 67%, compared to NCL-X.