The first asynchronous microprocessor: the test results
ACM SIGARCH Computer Architecture News
Design of delay insensitive circuits using multi-ring structures
EURO-DAC '92 Proceedings of the conference on European design automation
Automatic technology mapping for generalized fundamental-mode asynchronous designs
DAC '93 Proceedings of the 30th international Design Automation Conference
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Digital systems engineering
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Hazard-non-increasing gate-level optimization algorithms
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Coping with The Variability of Combinational Logic Delays
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Asynchronous two-level logic of reduced cost
DDECS '09 Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems
Designing Asynchronous Circuits using NULL Convention Logic (NCL)
Designing Asynchronous Circuits using NULL Convention Logic (NCL)
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail synchronous Boolean network of complex (AND-OR) nodes. Next, the transformation into a dual-rail Boolean network is done. Each node is minimized under the formulated constraint to ensure hazard-free implementation. Then the technology dependent mapping procedure is applied. The MCNC and ISCAS benchmark sets are processed and the area overhead with respect to the synchronous implementation is evaluated. The implementations of the asynchronous logic obtained using the proposed (with AND-OR nodes) and the state-of-the-art (nodes are designed based on DIMS, direct logic and NCL) network structures are compared. A method, where nodes are designed as simple (NAND, NOR, etc.) gates is chosen for a detailed comparison. In our approach, the number of completion detection logic inputs is reduced significantly, since the number of nodes that should be supplied with the completion detection is less than in the case of the network structure that is based on simple gates. As a result, the improvement in sense of the total complexity and performance is obtained.