Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations

Authors:
Haixia Gao;Yintang Yang;Xiaohua Ma;Gang Dong
Affiliations:
Xidian University, China;Xidian University, China;Xidian University, China;Xidian University, China
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

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Abstract

Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.