A New Switch Block for Segmented FPGAs

A crosstalk-aware timing-driven router for FPGAs

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays

Detailed routing architectures for embedded programmable logic IP cores

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays

FPGA switch block layout and evaluation

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

Analytical Framework for Switch Block Design

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

A Flexible Power Model for FPGAs

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

A detailed power model for field-programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Layout techniques for FPGA switch blocks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Routing architecture optimizations for high-density embedded programmable IP cores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A novel approach to the placement and routing problems for field programmable gate arrays

Applied Soft Computing

FPGA Architecture: Survey and Challenges

Foundations and Trends in Electronic Design Automation

Designing a 3-D FPGA: switch box architecture and thermal issues

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Using the minimum set of input combinations to minimize the area of local routing networks in logic clusters containing logically equivalent I/Os in FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

The effect of multi-bit correlation on the design of field-programmable gate array routing resources

IEEE Transactions on Very Large Scale Integration (VLSI) Systems