Layout techniques for FPGA switch blocks

  • Authors:
  • Herman Schmit;Vikas Chandra

  • Affiliations:
  • Tabula Inc., Santa Clara, CA;Tabula Inc., Santa Clara, CA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2005

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Abstract

This paper presents abstract layout techniques for a variety of field-programmable gate array switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks and good results for large switch blocks. We show how it is possible to transform universal switch blocks into a subset architecture by using the decomposition property of universal switch blocks. This allows universal switch blocks to exploit the same layout methodologies as presented for subset architectures.