Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Technology mapping for FPGAs with embedded memory blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Speed and area tradeoffs in cluster-based FPGA architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A New Switch Block for Segmented FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Architectures and algorithms for field-programmable gate arrays with embedded memory
Architectures and algorithms for field-programmable gate arrays with embedded memory
Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architectures and algorithms for synthesizable embedded programmable logic cores
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Layout techniques for FPGA switch blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement challenges for structured ASICs
Proceedings of the 2008 international symposium on Physical design
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Automatic design of reconfigurable domain-specific flexible cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
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Recent years have seen a tremendous increase in the capacities and capabilities of Field-Programmable Gate Arrays (FPGA's). Much of this dramatic improvement has been the result of changes to the FPGAs' internal architectures. New architectural proposals are routinely generated in both academia and industry. For FPGA's to continue to grow, it is important that these new architectural ideas are fairly and accurately evaluated, so that those worthy ideas can be included in future chips. Typically, this evaluation is done using experimentation. However, the use of experimentation is dangerous, since it requires making assumptions regarding the tools and architecture of the device in question. If these assumptions are not accurate, the conclusions from the experiments may not be meaningful. In this paper, we investigate the sensitivity of FPGA architectural conclusions to experimental variations. To make our study concrete, we evaluate the sensitivity of four previously published and well-known FPGA architectural results: lookup-table size, switch block topology, cluster size, and memory size. It is shown that these experiments are significantly affected by the assumptions, tools, and techniques used in the experiments.