Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Microelectronic circuits, 2nd ed.
Microelectronic circuits, 2nd ed.
Field-programmable gate arrays
Field-programmable gate arrays
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A new high density and very low cost reprogrammable FPGA architecture
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
Using sparse crossbars within LUT
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Mixing buffers and pass transistors in FPGA routing architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Interconnect prediction for programmable logic devices
Proceedings of the 2001 international workshop on System-level interconnect prediction
RPack: routability-driven packing for cluster-based FPGAs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Interconnect enhancements for a high-speed PLD architecture
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Circuit design of routing switches
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Automatic transistor and physical design of FPGA tiles from an architectural specification
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Modular, Fabric-Specific Synthesis for Programmable Architectures
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Exploring Logic Block Granularity for Regular Fabrics
Proceedings of the conference on Design, automation and test in Europe - Volume 1
The Stratix II logic and routing architecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic block clustering of large designs for channel-width constrained FPGAs
Proceedings of the 42nd annual Design Automation Conference
Device and architecture co-optimization for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
Performance benefits of monolithically stacked 3D-FPGA
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
FPGA device and architecture evaluation considering process variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Communication-oriented design space exploration for reconfigurable architectures
EURASIP Journal on Embedded Systems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The amorphous FPGA architecture
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Efficient tree topology for FPGA interconnect network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extrinsic evolvable hardware on the RISA architecture
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Microprocessors & Microsystems
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA
Microelectronics Journal
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We use a fully timing-driven experimental flow [4] [15] in which a set of benchmark circuits are synthesized into different cluster-based [2] [3] [15] logic block architectures, which contain groups of LUTs and flip-flops. We look across all architectures with LUT sizes in the range of 2 inputs to 7 inputs, and cluster size from 1 to 10 LUTs. In order to judge the quality of the architecture we do both detailed circuit level design and measure the demand of routing resources for every circuit in each architecture.These experiments have resulted in several key contributions. First, we have experimentally determined the relationship between the number of inputs required for a cluster as a function of the LUT size (K) and cluster size (N). Second, contrary to previous results, we have shown that when the cluster size is greater than four, that smaller LUTs (size 2 and 3) are almost as area efficient as 4-input LUTs, as suggested in [11]. However, our results also show that the performance of FPGAs with these small LUT sizes is significantly worse (by almost a factor of 2) than larger LUTs. Hence, as measured by area-delay product, or by performance, these would be a bad choice. Also, we have discovered that LUT sizes of 5 and 6 produce much better area results than were previously believed. Finally, our results show that a LUT size of 4 to 6 and cluster size of between 4 and 10 provides the best area-delay product for an FPGA.