PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
The complexity of simple computer architectures
The complexity of simple computer architectures
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Using sparse crossbars within LUT
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A New Floorplanning Method for FPGA Architectural Research
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Bubble Partitioning for LUT-Based Sequential Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
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In this paper, we present a new retargetable macro generation strategy for LUT-based sequential circuits. It is a first part of a new design system for performing studies on arbitrary configurable architectures with repetitive structures. Besides retargetability, the main characteristics of our method are the interlocking of circuit partitioner and macro generator, further a fitting strategy, that performs routing before placement.