Introduction to algorithms
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Exploration of heterogeneous FPGA architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Performance analysis and optimization of high density tree-based 3d multilevel FPGA
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Physical design exploration of 3D tree-based FPGA architecture
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA
Microelectronics Journal
Impact of dual placement and routing on WDDL netlist security in FPGA
International Journal of Reconfigurable Computing
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This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butter y-Fat-Tree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results show that the Tree-based architecture can implement MCNC benchmark circuits with an average gain of 54% in total area compared with Mesh architecture.